
#ifndef _MPI_CMD_H_
#define _MPI_CMD_H_

#include "mpi_lib.h"

#ifdef  __cplusplus
extern "C"
{
#endif

#define SGKS_NUM_PIC_TYPES    3

typedef enum
{
	// Configuration commands
	SGKS_DSP_CMD_INTERRUPT_SETUP                          = 0x00001001,
	SGKS_DSP_CMD_H264_ENCODING_SETUP                      = 0x00001002,
	SGKS_DSP_CMD_JPEG_ENCODING_SETUP                      = 0x00001003,
	SGKS_DSP_CMD_H264_DECODING_SETUP                      = 0x00001004,
	SGKS_DSP_CMD_JPEG_DECODING_SETUP                      = 0x00001005,
	SGKS_DSP_CMD_RESET_OPERATION                          = 0x00001006,
	SGKS_DSP_CMD_VIDEO_OUTPUT_RESTART                     = 0x00001007,
	SGKS_DSP_CMD_H264_ENC_USE_TIMER                       = 0x00001008,
	SGKS_DSP_CMD_CHIP_SELECTION                           = 0x00001009,
	SGKS_DSP_CMD_HD_ECHO_SETUP                            = 0x0000100A,
	SGKS_DSP_CMD_SYSTEM_SETUP_INFO                        = 0x0000100B,
	SGKS_DSP_CMD_EIS_SWITCHVO_DURING_ENCODE               = 0x0000100C,
	SGKS_DSP_CMD_DEBUG_LEVEL_SETUP                        = 0x0000100D,
	SGKS_DSP_CMD_SYSTEM_PARAMETERS_SETUP                  = 0x0000100E,
	SGKS_DSP_CMD_SYSTEM_ICORE_FREQ_SETUP                  = 0x0000100F,

	SGKS_DSP_CMD_SENSOR_INPUT_SETUP                       = 0x00002001,
	SGKS_DSP_CMD_RGB_GAIN_ADJUSTMENT                      = 0x00002002,
	SGKS_DSP_CMD_VIGNETTE_COMPENSATION                    = 0x00002003,
	SGKS_DSP_CMD_AAA_STATISTICS_SETUP                     = 0x00002004,
	SGKS_DSP_CMD_LUMA_SHARPEN_SETUP                       = 0x00002005,
	SGKS_DSP_CMD_RGB_TO_RGB_SETUP                         = 0x00002006,
	SGKS_DSP_CMD_RGB_TO_YUV_SETUP                         = 0x00002007,
	SGKS_DSP_CMD_GAMMA_CURVE_LOOKUP                       = 0x00002008,
	SGKS_DSP_CMD_NOISE_FILTER_SETUP                       = 0x00002009,
	SGKS_DSP_CMD_BAD_PIXEL_CORRECT_SETUP                  = 0x0000200A,
	SGKS_DSP_CMD_VID_FADE_IN_OUT_SETUP                    = 0x0000200B,
	SGKS_DSP_CMD_CFA_DOMAIN_LEAKAGE_FILTER                = 0x0000200C,
	SGKS_DSP_CMD_MCTF_MV_STAB_SETUP                       = 0x0000200D,
	SGKS_DSP_CMD_SET_SLOW_SHUT_UP_SAMPL_RT                = 0x0000200E,
	SGKS_DSP_CMD_SET_REPEAT_FRM                           = 0x0000200F,
	SGKS_DSP_CMD_MCTF_GMV_SETUP                           = 0x00002010,
	SGKS_DSP_CMD_DIS_SETUP                                = 0x00002011,    //This command is used to setup the DIS algorithm paramete and related debug stuff.

	SGKS_DSP_CMD_SET_VI_CAPTURE_WIN                       = 0x00002100,
	SGKS_DSP_CMD_AMPLIFIER_LINEARIZATION                  = 0x00002101,
	SGKS_DSP_CMD_PIXEL_SHUFFLE                            = 0x00002102,
	SGKS_DSP_CMD_BLACK_LEVEL_CORRECTION_CONFIG            = 0x00002103,
	SGKS_DSP_CMD_BLACK_LEVEL_STATE_TABLES                 = 0x00002104,
	SGKS_DSP_CMD_BLACK_LEVEL_DETECTION_WINDOW             = 0x00002105,
	SGKS_DSP_CMD_FIXED_PATTERN_NOISE_CORRECTION           = 0x00002106,
	SGKS_DSP_CMD_CFA_NOISE_FILTER_INFO                    = 0x00002107,
	SGKS_DSP_CMD_DIGITAL_GAIN_SATURATION_LEVEL            = 0x00002108,
	SGKS_DSP_CMD_LOCAL_EXPOSURE                           = 0x00002109,
	SGKS_DSP_CMD_DEMOASIC_FILTER                          = 0x0000210A,
	SGKS_DSP_CMD_RGB_NOISE_FILTER                         = 0x0000210B,
	SGKS_DSP_CMD_COLOR_CORRECTION                         = 0x0000210C,
	SGKS_DSP_CMD_CHROMA_MEDIAN_FILTER_INFO                = 0x0000210D,
	SGKS_DSP_CMD_CHROMA_SCALE                             = 0x0000210E,
	SGKS_DSP_CMD_LUMA_SHARPENING                          = 0x0000210F,
	SGKS_DSP_CMD_AAA_STATISTICS_SETUP1                    = 0x00002110,
	SGKS_DSP_CMD_AAA_STATISTICS_SETUP2                    = 0x00002111,
	SGKS_DSP_CMD_AAA_PSEUDO_Y_SETUP                       = 0x00002112,
	SGKS_DSP_CMD_AAA_HISTORGRAM_SETUP                     = 0x00002113,
	SGKS_DSP_CMD_RAW_COMPRESSION                          = 0x00002114,
	SGKS_DSP_CMD_RAW_DECOMPRESSION                        = 0x00002115,
	SGKS_DSP_CMD_ROLLING_SHUTTER_COMPENSATION             = 0x00002116,
	SGKS_DSP_CMD_SET_ZOOM_FACTOR                          = 0x00002117,
	SGKS_DSP_CMD_AAA_STATISTICS_SETUP3                    = 0x00002118,
	SGKS_DSP_CMD_VIDEO_PREVIEW_SETUP                      = 0x00002119,
	SGKS_DSP_CMD_VI_RESET                                 = 0x0000211A,
	SGKS_DSP_CMD_ANTI_ALIASING                            = 0x0000211B,
	SGKS_DSP_CMD_FPN_CALIBRATION                          = 0x0000211C,
	SGKS_DSP_CMD_BLACK_LEVEL_GLOBAL_OFFSET                = 0x0000211D,
	SGKS_DSP_CMD_RGB_DIRECTIONAL_FILTER                   = 0x0000211E,
	SGKS_DSP_CMD_HDR_MIXER                                = 0x0000211F,
	SGKS_DSP_CMD_LUMA_SHARPENING_LINEARIZATION            = 0x00002120,
	SGKS_DSP_CMD_LUMA_SHARPENING_FIR_CONFIG               = 0x00002121,
	SGKS_DSP_CMD_LUMA_SHARPENING_LNL                      = 0x00002122,
	SGKS_DSP_CMD_LUMA_SHARPENING_TONE                     = 0x00002123,
	SGKS_DSP_CMD_MULTI_STREAM_VIDEO_PREVIEW               = 0x00002124,
	SGKS_DSP_CMD_ENA_SECOND_STREAM_ENCODE                 = 0x00002125,
	SGKS_DSP_CMD_SET_ALPHA_CHANNEL                        = 0x00002126,
	SGKS_DSP_CMD_MODIFY_FRAME_BUFFER                      = 0x00002127,
	SGKS_DSP_CMD_SET_ACT_WIN_CENTER                       = 0x00002128,
	SGKS_DSP_CMD_SET_WARP_CONTROL                         = 0x00002129,
	SGKS_DSP_CMD_EARLY_WB_GAIN                            = 0x0000212A,
	SGKS_DSP_CMD_LUMA_SHARPENING_EDGE_CONTROL             = 0x00002130,
	SGKS_DSP_CMD_LUMA_SHARPENING_BLEND_CONTROL            = 0x00002131,
	SGKS_DSP_CMD_LUMA_SHARPENING_LEVEL_CONTROL            = 0x00002132,
	SGKS_DSP_CMD_LUMA_SHARPENING_MISC_CONTROL             = 0x00002133,
	SGKS_DSP_CMD_AAA_EARLY_WB_GAIN                        = 0x00002134,

	// H264/JPEG encoding mode commands
	SGKS_DSP_CMD_VIDEO_PREPROCESSING                      = 0x00003001,
	SGKS_DSP_CMD_FAST_AAA_CAPTURE                         = 0x00003002,
	SGKS_DSP_CMD_H264_ENCODE                              = 0x00003004,
	SGKS_DSP_CMD_H264_ENCODE_FROM_MEMORY                  = 0x00003005,
	SGKS_DSP_CMD_H264_BITS_FIFO_UPDATE                    = 0x00003006,
	SGKS_DSP_CMD_ENCODING_STOP                            = 0x00003007,
	SGKS_DSP_CMD_MODIFY_CMD_DLY                           = 0x00003008,

	SGKS_DSP_CMD_STILL_CAPTURE                            = 0x00004001,
	SGKS_DSP_CMD_JPEG_ENCODE_RESCALE_FROM_MEMORY          = 0x00004002,
	SGKS_DSP_CMD_JPEG_BITS_FIFO_UPDATE                    = 0x00004003,
	SGKS_DSP_CMD_FREE_RAW_YUV_PIC_BUFFER                  = 0x00004004,
	SGKS_DSP_CMD_JPEG_RAW_YUV_STOP                        = 0x00004005,
	SGKS_DSP_CMD_MJPEG_ENCODE                             = 0x00004006,
	SGKS_DSP_CMD_VID_FADE_IN_OUT                          = 0x00004007,
	SGKS_DSP_CMD_MJPEG_ENCODE_WITH_H264                   = 0x00004008,
	SGKS_DSP_CMD_OSD_INSERT                               = 0x00004009,
	SGKS_DSP_CMD_YUV422_CAPTURE                           = 0x00004010,
	SGKS_DSP_CMD_SEND_CAVLC_RESULT                        = 0x00004011,
	SGKS_DSP_CMD_STILL_CAPTURE_IN_REC                     = 0x00004012,      // Z.ZHOU added for still capture during active recording
	SGKS_DSP_CMD_OSD_BLEND                                = 0x00004013,
	SGKS_DSP_CMD_INTERVAL_CAPTURE                         = 0x00004014,
	SGKS_DSP_CMD_STILL_CAPTURE_ADV                        = 0x00004015,

	// H264/JPEG decode mode commnads
	SGKS_DSP_CMD_H264_DECODE                              = 0x00005002,
	SGKS_DSP_CMD_JPEG_DECODE                              = 0x00005003,
	SGKS_DSP_CMD_RAW_PICTURE_DECODE                       = 0x00005004,
	SGKS_DSP_CMD_RESCALE_POSTPROCESSING                   = 0x00005005,
	SGKS_DSP_CMD_H264_DECODE_BITS_FIFO_UPDATE             = 0x00005006,
	SGKS_DSP_CMD_H264_PLAYBACK_SPEED                      = 0x00005007,
	SGKS_DSP_CMD_H264_TRICKPLAY                           = 0x00005008,
	SGKS_DSP_CMD_DECODE_STOP                              = 0x00005009,
	SGKS_DSP_CMD_MULTI_SCENE_DECODE                       = 0x00005010,
	SGKS_DSP_CMD_CAPTURE_VIDEO_PICTURE                    = 0x00005011,
	SGKS_DSP_CMD_CAPTURE_STILL_PICTURE                    = 0x00005012,
	SGKS_DSP_CMD_JPEG_FREEZE                              = 0x00005013,
	SGKS_DSP_CMD_MULTI_SCENE_SETUP                        = 0x00005014,
	SGKS_DSP_CMD_MULTI_SCENE_DECODE_ADV                   = 0x00005015,
	SGKS_DSP_CMD_JPEG_DECODE_THUMBNAIL_WARP               = 0x00005016,
	SGKS_DSP_CMD_MULTI_SCENE_DECODE_ADV_2                 = 0x00005017,
	SGKS_DSP_CMD_DECODE_RESCALE                           = 0x00005018,

	// IP CAM commands
	SGKS_DSP_CMD_IPCAM_VIDEO_PREPROCESSING                = 0x00006001,
	SGKS_DSP_CMD_IPCAM_VIDEO_CAPTURE_PREVIEW_SIZE_SETUP   = 0x00006002,
	SGKS_DSP_CMD_IPCAM_VIDEO_ENCODE_SIZE_SETUP            = 0x00006003,
	SGKS_DSP_CMD_IPCAM_REAL_TIME_ENCODE_PARAM_SETUP       = 0x00006004,
	SGKS_DSP_CMD_IPCAM_VIDEO_FORCED_IDR                   = 0x00006005,
	SGKS_DSP_CMD_IPCAM_VIDEO_SYSTEM_SETUP                 = 0x00006006,
	SGKS_DSP_CMD_IPCAM_OSD_INSERT                         = 0x00006007,
	SGKS_DSP_CMD_IPCAM_SET_PRIVACY_MASK                   = 0x00006008,
	SGKS_DSP_CMD_IPCAM_QP_RATIO                           = 0x00006009,
	SGKS_DSP_CMD_IPCAM_PIP_CONFIG                         = 0x0000600A,
    SGKS_DSP_CMD_IPCAM_SWITCH_SRC                         = 0x0000600B,


	// VO commands
	SGKS_DSP_CMD_VO_MIXER_SETUP                           = 0x00007001,
	SGKS_DSP_CMD_VO_VIDEO_SETUP                           = 0x00007002,
	SGKS_DSP_CMD_VO_DEFAULT_IMG_SETUP                     = 0x00007003,
	SGKS_DSP_CMD_VO_OSD_SETUP                             = 0x00007004,
	SGKS_DSP_CMD_VO_OSD_BUFFER_SETUP                      = 0x00007005,
	SGKS_DSP_CMD_VO_OSD_CLUT_SETUP                        = 0x00007006,
	SGKS_DSP_CMD_VO_DISPLAY_SETUP                         = 0x00007007,
	SGKS_DSP_CMD_VO_TV_SETUP                              = 0x00007008,
	SGKS_DSP_CMD_VO_RESET                                 = 0x00007009,
	SGKS_DSP_CMD_VO_DISPLAY_CSC_SETUP                     = 0x0000700A,
	SGKS_DSP_CMD_VO_DIGITAL_OUTPUT_MODE_SETUP             = 0x0000700B,

	// These SGKS_* commands are for sgks experimental use only
	SGKS_DSP_CMD_CFA_NOISE_FILTER                         = 0x0000f001,
	SGKS_DSP_CMD_DIGITAL_GAIN_SATURATION                  = 0x0000f002,
	SGKS_DSP_CMD_CHROMA_MEDIAN_FILTER                     = 0x0000f003,
	SGKS_DSP_CMD_LUMA_DIRECTIONAL_FILTER                  = 0x0000f004,
	SGKS_DSP_CMD_LUMA_SHARPEN                             = 0x0000f005,
	SGKS_DSP_CMD_MAIN_RESAMPLER_BANDWIDTH                 = 0x0000f006,
	SGKS_DSP_CMD_CFA_RESAMPLER_BANDWIDTH                  = 0x0000f007,

	SGKS_DSP_CMD_DEBUG_0                                  = 0x0000ff00,
	SGKS_DSP_CMD_DEBUG_1                                  = 0x0000ff01,
	SGKS_DSP_CMD_AAA_STATISTICS_DEBUG                     = 0x0000ff02,
	SGKS_DSP_CMD_SPECIAL                                  = 0x0000ff03,
	SGKS_DSP_CMD_AAA_STATISTICS_DEBUG1                    = 0x0000ff04,
	SGKS_DSP_CMD_AAA_STATISTICS_DEBUG2                    = 0x0000ff05,
	SGKS_DSP_CMD_BAD_PIXEL_CROP                           = 0x0000ff06,
	SGKS_DSP_CMD_DEBUG_2                                  = 0x0000ff07,
	SGKS_DSP_CMD_DEBUG_3                                  = 0x0000ff08,
	SGKS_DSP_CMD_UPDATE_ICORE_CONFIG                      = 0x0000ff09,
	SGKS_DSP_CMD_REAL_TIME_RATE_MODIFY                    = 0x0000ff0a,
	SGKS_DSP_CMD_STOP_FATAL_FW                            = 0x0000ffa0,
} sgks_dsp_cmd_e;


// SGKS_DSP_CMD_CHIP_SELECTION                          = 0x00001009,
typedef struct sgks_dsp_cmd_chip_select
{
	u32 cmd_code;
	u8  chip_type;
} sgks_dsp_cmd_chip_select_s;


// SGKS_DSP_CMD_IPCAM_VIDEO_SYSTEM_SETUP                = 0x00006006,
typedef struct sgks_dsp_cmd_ipcam_video_system_setup
{
	u32 cmd_code;
	u16 main_max_width;
	u16 main_max_height;
	u16 preview_A_max_width;
	u16 preview_A_max_height;
	u16 preview_B_max_width;
	u16 preview_B_max_height;
	u16 preview_C_max_width;
	u16 preview_C_max_height;
	u8  stream_0_max_GOP_M;
	u8  stream_1_max_GOP_M;
	u8  stream_2_max_GOP_M;
	u8  stream_3_max_GOP_M;
	u8  stream_0_max_GOP_N;
	u8  stream_1_max_GOP_N;
	u8  stream_2_max_GOP_N;
	u8  stream_3_max_GOP_N;
	u8  stream_0_max_advanced_quality_model;
	u8  stream_1_max_advanced_quality_model;
	u8  stream_2_max_advanced_quality_model;
	u8  stream_3_max_advanced_quality_model;
	u16 stream_0_max_width;
	u16 stream_0_max_height;
	u16 stream_1_max_width;
	u16 stream_1_max_height;
	u16 stream_2_max_width;
	u16 stream_2_max_height;
	u16 stream_3_max_width;
	u16 stream_3_max_height;
	u32 MCTF_possible       :  1;
	u32 max_num_streams     :  3;
	u32 max_num_cap_sources :  2;
	u32 use_1Gb_DRAM_config :  1;
	//u32 reserved1           : 25;
#if 0 //SH-L   
	U32 reserved1 : 25 ;
#else
	u32 cap_buf_cush: 2;	//0-3	//sam start
	u32 use_5_buffer : 1;
	u32 use_dsp_engine : 1;	//sam end
	u32 temporal_filter_mode : 2;
//u32 reserved2 : 19 ;
	u32 cvbs_buf_nums : 5;
	u32 reserved2 : 14;
#endif

	u16 raw_max_width;
	u16 raw_max_height;
} sgks_dsp_cmd_ipcam_video_system_setup_s;



// SGKS_DSP_CMD_SET_VI_CAPTURE_WIN                      = 0x00002100,
typedef struct sgks_dsp_cmd_vi_cap_win
{
	u32 cmd_code;
	u32 S_Control_reset                 :  1;   // 0: no op  1: reset video in
	u32 S_Control_enable                :  1;   // 0: idle   1: enable video in
	u32 S_Control_win_en                :  1;   // enable capture window. automatic reset at the end of each capture
	u32 S_Control_data_edge             :  1;   // Data clock edge. 0: valid on rising edge of sensor clock
	//                  1: valid on falling edge of sensor clock
	u32 S_Control_mastSlav_mod          :  2;   // Bit [5:4] forms the following combination:
	// 2b00: undefined
	// 2b01: slave mode
	// 2b10: master mode
	// 2b11: undefined
	u32 S_Control_data_emb_sync         :  1;   // sync code embedded in data. When set in master mode,
	// this indicates sensors have embedded sync code while
	// receiving seperate sync signals (Sony specific).
	u32 S_Control_data_emb_sync_mode    :  1;   // Embedded sync mode. 0: ITU-656 style(8-bit) 1: ITU-656 style(full data range)
	u32 S_Control_data_emb_sync_loc     :  2;   // Embedded sync code location (2-pixel wide input only).
	// 2b00: embedded sync code carried on the lower pixel
	// 2b01: embedded sync code carried on the upper pixel
	// 2b1x: embedded sync code carried on both pixels [should programed to 2b1x for serial sensor interface modes]
	u32 S_Control_data_vs_pol           :  1;   // vsync polarity. 0: active high (rising edge signals start)  1: active low (falling edge signals start)
	u32 S_Control_data_hs_pol           :  1;   // hsync polarity. 0: active high (rising edge signals start)  1: active low (falling edge signals start)
	u32 S_Control_data_field0_pol       :  1;   // 0: field 0 has ID set to 0 with wen assertion   1:field 0 has ID set to 1 with wen assertion
	u32 S_Control_data_sony_field_mode  :  1;   // 0: normal field mode   1: Sony-specific field mode. The first field of a multi-field readout in Sony CCD/TG is indicated by the state of EXP/ID pin at the first assertion of WEN/FLD
	u32 S_Control_data_ecc_enable       :  1;   // 656 error correction enable {including the sync code words in serial sensor mode]
	u32 S_Control_data_hsync_mask       :  1;   // 0: Toggle hsync during vertical blanking    1: No hsync toggle during vertical blanking
	// reg 0x01: 0x06
	// input mode[4:0]
	u32 S_InputConfig_pad_type          :  1;   // 0: LVCMOS  1: LVDS
	u32 S_InputConfig_data_rate         :  1;   // 0: SDR    1: DDR
	u32 S_InputConfig_data_width        :  1;   // 0: 1-pixel wide  1: 2-pixel wide [should be programed to 1 (2-pixel wide) for serial sensor interface modes]
	u32 S_InputConfig_input_source      :  1;   // 0: from LVDS (lvds_idsp_sdata)     1: from GPIO (iopad_idsp_sdata). Input source and pad type forms three combinations:-LVDS source, LVDS pad.-LVDS source, LVCMOS pad.-GPIO source. (Pad type makes no difference.)
	u32 S_InputConfig_RGB_YUV           :  1;   // 0: RGB input    1: YUV input
	// The following are legal combinations for input mode (x: 0 or 1, -: no effect):
	// x000x:SDR,1-pixel wide RGB/YUV data, from lvds_idsp_sdata[13:0]
	// x001x:DDR,1-pixel wide RGB/YUV data, from lvds_idsp_sdata[27:0]
	// x0100:SDR,2-pixel wide RGB/YUV data, from lvds_idsp_sdata[27:0]
	// x0110:DDR,2-pixel wide RGB/YUV data, from lvds_idsp_sdata[55:0]
	// 110--:1-pixel wide YUV data, from iopad_idsp_sdata[7:0]
	// 111--:2-pixel wide YUV data, from iopad_idsp_sdata[15:0]
	u32 S_InputConfig_Source_pixel_data_width   :  2;   // Source pixel data width. VIN aligns all pixel values to MSB at output.
	// For example, 8-bit source means left shift by 6, 14-bit source means no shift,
	// etc. YUV data coming from GPIO must be 8-bit wide. (Hardware ignores the configuration.)
	// 2b00: 8-bit  2b01: 10-bit    2b10: 12-bit    2b11: 14-bit
	u32 S_InputConfig_YUV_input_order   :  2;   // YUV input order
	// For 1-pixel wide YUV data
	// 00:Cr,Y0,Cb,Y1,
	// 01:Cb,Y0,Cr,Y1,
	// 10:Y0,Cr,Y1,Cb,
	// 11:Y0,Cb,Y1,Cr,
	// For 2-pixel wide YUV data
	// 00:{Cr,Y},{Cb,Y},
	// 01:{Cb,Y},{Cr,Y},
	// 10:{Y,Cr},{Y,Cb},
	// 11: {Y, Cb}, {Y, Cr},
	u32 S_InputConfig_Number_of_active_SLVS_lanes   :  2;   // Number of active SLVS lanes
	// 2b00: 4 lanes; 2b01: 8 lanes; 2b10: 12 lanes; 2b11: 16 lanes)
	u32 S_InputConfig_Serial_sensor_interface_mode  :  1;   // Serial sensor interface mode (Micron and Sony)
	u32 S_InputConfig_Sony_serial_sensor_interface_mode :  1;   // Sony serial sensor interface mode
	u32 S_InputConfig_VIN_clock_select  :  1;   // VIN clock select - use sensor or bit clock instead of IDSP clock
	u32 S_MIPI_Config                   :  2;   // reserved


	// reg 0x02: 0x08
	// Status register: Write logic 1 to the status register clears the corresponding bit.
	u32 S_Status_vsync              :  1;   // begin of frame detected
	u32 S_Status_trig0              :  1;   // trigger 0 status. 0: no trigger/ 1: triggered
	u32 S_Status_trig1              :  1;   // trigger 1 status. 0: no trigger/ 1: triggered
	u32 S_Status_ovfl               :  1;   // synchronous FIFO overflow. 0: no overflow/ 1: overflow occurred
	u32 S_Status_shortl             :  1;   // early hsync detected
	u32 S_Status_shortf             :  1;   // early vsync detected
	u32 S_Status_field              :  3;   // current video field (read only).
	u32 S_Status_no_hsync           :  1;   // no hsync detected (time out)
	u32 S_Status_no_vsync           :  1;   // no vsync detected (time out)
	u32 S_Status_idsp_ahb_vsync     :  1;   // frame end signal to ARM
	u32 S_Status_idsp_ahb_mst_vsync :  1;   // master mode frame end signal to ARM
	u32 S_Status_idsp_ahb_last_pxl  :  1;   // capture window end signal to ARM
	u32 S_Status_ecc_uncorrectable  :  1;   // uncorrectable 656 errors
	u32 S_Status_program_error      :  1;   // illegal programming detected. Currently the reported error includes:Master mode, active region exceeds frame region
	// reg 0x03: 0x0A
	// Vertical active region width (master mode only)
	u32 S_Vwidth                    : 14;   // vsync pulse width in unit of lines
	u32                             :  2;   // reserved

	// reg 0x04: 0x0C
	// Horizontal active region width (master mode only).
	u32 S_Hwidth                    : 14;   // hsync pulse width in unit of pixels
	u32                             :  2;   // reserved
	// reg 0x05: 0x0E
	u32 S_Hoffset_top               : 14;   //
	u32                             :  2;   // reserved

	// reg 0x06: 0x10
	u32 S_Hoffset_bot               : 14;   //
	u32                             :  2;   // reserved
	// reg 0x07: 0x12
	// Frame size, vertical (master mode only)
	u32 S_V                         : 14;   // Number of lines per field
	u32                             :  2;   // reserved

	// reg 0x08: 0x14
	// Frame size, horizontal (in master mode only)
	u32 S_H                         : 14;   // Number of pixels per line
	u32                             :  2;   // reserved
	// reg 0x09: 0x16
	// Minimum frame size, vertical (slave mode only)
	u32 S_MinV                      : 14;   // number of lines per field
	u32                             :  2;   // reserved

	// reg 0x0A: 0x18
	// Minimum frame size, horizontal (slave mode only)
	u32 S_MinH                      : 14;   // number of pixels per line
	u32                             :  2;   // reserved
	// reg 0x0B: 0x1A
	// Trigger 0 control
	u32 S_Trigger0Start_startline   : 14;   // startline. Assert trigger at the assertion of hsync of the n-thline of the frame,
	// where n = startline (counting from 1st line active region)
	u32 S_Trigger0Start_pol         :  1;   // polarity. 0: active low trigger/ 1: active high trigger
	u32 S_Trigger0Start_enable      :  1;   // 0: trigger disabled/ 1: trigger enabled

	// reg 0x0C: 0x1C
	// Trigger 0 control
	u32 S_Trigger0End_startline     : 14;   // lastline. Deassert trigger at the assertion of hsync of the n-thline of the frame,
	// where n = lastline (counting from 1st line active region)
	u32                             :  2;   // reserved
	// reg 0x0D: 0x1E
	// Trigger 1 control
	u32 S_Trigger1Start_startline   : 14;   // startline. Assert trigger at the assertion of hsync of the n-thline of the frame,
	// where n = startline (counting from 1st line active region)
	u32 S_Trigger1Start_pol         :  1;   // polarity. 0: active low trigger/ 1: active high trigger
	u32 S_Trigger1Start_enable      :  1;   // 0: trigger disabled/ 1: trigger enabled

	// reg 0x0E: 0x20
	// Trigger 1 control
	u32 S_Trigger1End_startline     : 14;   // lastline. Deassert trigger at the assertion of hsync of the n-thline of the frame,
	// where n = lastline (counting from 1st line active region)
	u32                             :  2;   // reserved
	// reg 0x0F: 0x22
	// VOUT synchronization control
	u32 S_VoutStart0_startline      : 14;   // startline. Synchronization signal is asserted for the duration of the n-th line,
	// where n = startline (counting from 1st line active region)
	u32                             :  1;   // reserved
	u32 S_VoutStart0_disable_field_check    :  1;   // 0: synchronization signal is set on even field/ 1: synchronization signal is set on each field

	// reg 0x10: 0x24
	// VOUT synchronization control
	u32 S_VoutStart1_startline      : 14;   // startline. Synchronization signal is asserted for the duration of the n-th line,
	// where n = startline (counting from 1st line active region)
	u32                             :  1;   // reserved
	u32 S_VoutStart1_disable_field_check    :  1;   // 0: synchronization signal is set on even field/ 1: synchronization signal is set on each field
	// reg 0x11: 0x26
	// Capture window control, vertical start
	u32 S_CapStartV                 : 14;   // Start vertical location of capture window
	u32                             :  2;   // reserved

	// reg 0x12: 0x28
	// Capture window control, horizontal start
	u32 S_CapStartH                 : 14;   // Start horizontal location of capture window
	// In 8 channel , Sony serial sensor mode, the capture window should start 4
	// pixels after the SAV (i.e. exclude the 4 pixels added by the receiver at the
	// beginning of every line which are not part of the original active line)
	u32                             :  2;   // reserved
	// reg 0x13: 0x2A
	// Capture window control, vertical end
	u32 S_CapEndV                   : 14;   // End vertical location of capture window
	u32                             :  2;   // reserved

	// reg 0x14: 0x2C
	// Capture window control, horizontal end
	u32 S_CapEndH                   : 14;   // End horizontal location of capture window
	// In 8 channel, Sony serial sensor mode, the capture window should end 4 pixels
	// before the EAV sync code to exclude the additional sync code pixels.
	u32                             :  2;   // reserved
	// reg 0x15: 0x2E
	// All-zero embedded sync horizontal blank interval length
	u32 S_BlankLengthH              : 14;   // Blank interval length in sensor clock cycles
	u32                             :  2;   // reserved

	// reg 0x16: 0x30
	// Vsync timeout limit (lower 16 bits) and also EAV column for SLVS mode.
	u32 S_TimeoutVLow               : 16;   // SLVS mode programing notes:Should be integer multiple of 4 and does not count SAV/EAV sync code pixels
	// reg 0x17: 0x32
	// Vsync timeout limit (upper 16 bits)
	u32 S_TimeoutVHigh              : 16;   //

	// reg 0x18: 0x34
	// Hsync timeout limit (lower 16 bits) and also Horizontal line length (SAV-to-SAV distance) in SLVS mode.
	u32 S_TimeoutHLow               : 16;   // SLVS mode programing notes:Should be integer multiple of 4 and does not count SAV/EAV sync code pixels
	// reg 0x19: 0x36
	// Hsync timeout limit (lower 16 bits)
	u32 S_TimeoutHHigh              : 16;   //

	// reg 0x19: 0x38
	u32 S_mipi_cfg1                 : 16;   //
	// reg 0x1A: 0x3A
	u32 S_mipi_cfg2                 : 16;   //

	// reg 0x1B: 0x3C
	u32 S_mipi_bdphyctl             : 16;   //
	// reg 0x1C: 0x3E
	u32 S_mipi_sdphyctl             : 16;   //
	// reg 0x1E
	u32 S_mipi_timing1             : 16;   //
	//reg 0x1F
	u32 S_mipi_timing2             : 16;   //

} sgks_dsp_cmd_vi_cap_win_s;

typedef struct sgks_application_mode
{
	u32 multiple_stream : 7;    // 0:single stream, 1: multiple stream
	u32 power_mode      : 1;    // 0: high power, 1: low power
} sgks_application_mode_s;


typedef enum
{
	SGKS_DV_APP_MODE          = 0,
	SGKS_DVR_APP_MODE         = 1,
	SGKS_IPCAM_APP_MODE       = 2,
	SGKS_IPCAM_APP_MODE_NUM,
} sgks_app_mode_e;

//0x100b
typedef struct sgks_dsp_cmd_system_setup_info
{
	u32 cmd_code;
	u32 preview_A_type              : 8;
	u32 preview_B_type              : 8;
	u32 voA_osd_blend_enabled       : 1;   /* if set, Mixing section of VOA is used for DRAM to DRAM OSD blending */
	u32 voB_osd_blend_enabled       : 1;   /* if set, Mixing section of VOB is used for DRAM to DRAM OSD blending */
	u32 coded_bits_interrupt_enabled: 1;   /* if set, VOA interrupt is generated to ARM for every H.264/MJPEG coded frame written to the bits FIFO */
	u32 pip_size_preview_enabled    : 1;   /* if set, preview A/B/C may be downscaled to PiP resolution (ie: preveiw width < 320) */
	u32 low_delay_enabled           : 1;   /* if set, ICORE will not insert one dummy frame latency after MCTF to compensate for OSD insertion.  Only for M=1 case. */
	u32 padding                     : 11;
	sgks_application_mode_s   sub_mode_sel;   //0: Camcorder mode (single-stream encoder) 1: DVR mode (multiple-stream encoder)
	u8  num_yuv_src;                    // number of input YUV sources muxed together.
	u8  resv_1;
	u16 resv_2;
	u32 audio_clk_freq;
	u32 icore_freq;
	u16 sensor_HB_pixel;
	u16 sensor_VB_pixel;
} sgks_dsp_cmd_system_setup_info_s;


// SGKS_DSP_CMD_IPCAM_VIDEO_CAPTURE_PREVIEW_SIZE_SETUP  = 0x00006002,
typedef struct sgks_dsp_cmd_ipcam_capture_preview_size_setup
{
	u32 cmd_code;
	u32 capture_source      :  2;
	u32 output_scan_format  :  1;
	u32 deinterlace_mode    :  2;
	u32 disabled            :  1;
	u32 Reserved1           : 26;
	u16 cap_width;
	u16 cap_height;
	u16 input_win_offset_x;
	u16 input_win_offset_y;
	u16 input_win_width;
	u16 input_win_height;

	u16 enable_uv_offset;
	u16 input_win_offset_uv_x;
	u16 input_win_offset_uv_y;	
} sgks_dsp_cmd_ipcam_capture_preview_size_setup_s;


// SGKS_DSP_CMD_SENSOR_INPUT_SETUP                      = 0x00002001,
typedef struct sgks_dsp_cmd_sensor_input_setup
{
	u32 cmd_code;
	u8  sensor_id;
	u8  field_format;
	u8  sensor_resolution;
	u8  sensor_pattern;
	u8  first_line_field_0;
	u8  first_line_field_1;
	u8  first_line_field_2;
	u8  first_line_field_3;
	u8  first_line_field_4;
	u8  first_line_field_5;
	u8  first_line_field_6;
	u8  first_line_field_7;
	u32 sensor_readout_mode;
} sgks_dsp_cmd_sensor_input_setup_s;

// SGKS_DSP_CMD_VIDEO_PREPROCESSING                     = 0x00003001,
typedef struct sgks_dsp_cmd_video_preproc
{

	u32 cmd_code;

	u32 input_format    :  8;
	u32 sensor_id       :  8;
	u32 keep_states     :  8;
	u32 vi_frame_rate   :  8;

	u16 vidcap_w;
	u16 vidcap_h;

	u16 main_w;
	u16 main_h;

	u16 encode_w;
	u16 encode_h;

	u16 encode_x;
	u16 encode_y;

	u16 preview_w_A;
	u16 preview_h_A;

	u32 input_center_x;
	u32 input_center_y;
	u32 zoom_factor_x;
	u32 zoom_factor_y;
	u32 aaa_data_fifo_start;
	u32 sensor_readout_mode;

	u8 noise_filter_strength;
	u8 image_stabilize_strength;
	u8 bit_resolution;
	u8 bayer_pattern;
#define    PREVIEW_FORMAT_PROGRESS                  0
#define    PREVIEW_FORMAT_INTERLACE                 1
#define    PREVIEW_FORMAT_DEFAULT_IMAGE_PROGRESS    2
#define    PREVIEW_FORMAT_DEFAULT_IMAGE_INTERLACE   3
#define    PREVIEW_FORMAT_PROGRESS_TOP_FIELD        4
#define    PREVIEW_FORMAT_PROGRESS_BOT_FIELD        5
#define    PREVIEW_FORMAT_NO_OUTPUT                 6


	u8 preview_format_A     :  4;
	u8 preview_format_B     :  3;
	u8 no_pipelineflush     :  1;
	u8 preview_frame_rate_A;
	u16 preview_w_B;

	u16 preview_h_B;
	u8 preview_frame_rate_B;
	u8 preview_A_en         :  4; // 0: dram, 1: smem
	u8 preview_B_en         :  4; // 0: dram, 1: smem

	u16 horizontal_channel_number; // number of channels (streams) displayed on horizontal direction in preview window.
	u16 vertical_channel_number;    //number of channels (streams) displayed on vertical direction in preview window.

	u8 vi_frame_rate_ext;
	//u8 vdsp_int_factor;
	u8 dsp2_int_factor;
	u8 main_out_frame_rate;
	u8 main_out_frame_rate_ext;

	u8 vid_skip;                     //used to skip N start frames in VIN capture to avoid bad frames
	u8 EIS_enable               :  1;        //Used to inidcate that EIS will be used.
	u8 DIS_enable               :  1;        //Used to indicate that DIS will be used
	u8 Vert_WARP_enable         :  1;        //Used to indicate that Vertical  WARP will be used
	u8 no_vi_reset_exiting     :  1;        //Used to indicate that we do not need to resetting vin and need to wait
	//out the vin before exiting VIDEO mode to TIMER mode
	u8 support_cfa_out_win_2129 :  1;    //Enable teh CFA output window support in ucode.
	//This one is only useful for non DIS pipeline
	u8 oversampling_disabled    :  1;        // When set to 1, oversampling is disabled
	u8 hd_sdi_mode              :  1;     // when set to 1, HD-SDI mode
	u8 reserved                 :  1;

	u8 prevA_drv_voutB;                      //when enable , prevB drive voutA ,automatically
	u8 reserved_2;


	u32 cmdReadDly;                // Used to indicate the turbo command time related to normal interrrupts.
	// First bit indicate its direction,
	// 1: before the VDSP interrupt, i.e., turbo command deadline is the
	// absolute value of cmdReadDly's audio clk before the next normal interrupts.
	// 0: after the VDSP interrutps, i.e., turbo command deadline is the
	// absolute value of cmdReadDly's audio clk after the next normal interrutps.
	// new fields for preview source window parameters of preview A and B
	// x/y offset is relative to the upper left
	// corner of the Main window.
	u16 preview_src_w_A;
	u16 preview_src_h_A;
	u16 preview_src_x_offset_A;
	u16 preview_src_y_offset_A;
	u16 preview_src_w_B;
	u16 preview_src_h_B;
	u16 preview_src_x_offset_B;
	u16 preview_src_y_offset_B;

	u16 cvbs_input_width;
	u16 cvbs_input_height;

	u8 mipi_resolution: 4;
	u8 cvbs_interleave: 4;
	u8 prevC_src; //#define SRC_SENSOR 0  //#define SRC_CVBS 1
	u8 prevA_src;
	u8 prevB_src;
} sgks_dsp_cmd_video_preproc_s;



// VO commands
// SGKS_DSP_CMD_VO_MIXER_SETUP                          = 0x00007001,
typedef struct sgks_dsp_cmd_vo_mixer_setup
{
	u32 cmd_code;

	u16 vo_id;
	u8  interlaced;
	u8  frm_rate;

	u16 act_win_width;
	u16 act_win_height;

	u8  back_ground_v;
	u8  back_ground_u;
	u8  back_ground_y;
	u8  reserved;

	u8  highlight_v;
	u8  highlight_u;
	u8  highlight_y;
	u8  highlight_thresh;
	///////////////////////////////////////
	u8  highlight_osd2_v;
	u8  highlight_osd2_u;
	u8  highlight_osd2_y;
	u8  highlight_osd2_thresh;
} sgks_dsp_cmd_vo_mixer_setup_s;


// SGKS_DSP_CMD_VO_VIDEO_SETUP                          = 0x00007002,
typedef struct sgks_dsp_cmd_vo_video_setup
{
	u32 cmd_code;
	u16 vo_id;
	u8  en;
	u8  src;
	u8  flip;
	u8  rotate;
	u8  data_src;
	u8  reserved;
	u16 win_offset_x;
	u16 win_offset_y;
	u16 win_width;
	u16 win_height;
	u32 default_img_y_addr;
	u32 default_img_uv_addr;
	u16 default_img_pitch;
	u8  default_img_repeat_field;
	u8  reserved2;
} sgks_dsp_cmd_vo_video_setup_s;


// SGKS_DSP_CMD_VO_DEFAULT_IMG_SETUP                    = 0x00007003,
typedef struct sgks_dsp_cmd_vo_default_img_setup
{
	u32 cmd_code;
	u16 vo_id;
	u16 reserved;
	u32 default_img_y_addr;
	u32 default_img_uv_addr;
	u16 default_img_pitch;
	u8  default_img_repeat_field;
	//u8  reserved2;
	u8  mjpeg_yuv; //0:yuv420, 1:yuv422
	u16 mjpeg_width;
	u16 mjpeg_height;
	u32 newest_bank_daddr;
	u32 bank0_daddr;
	u16 video_offset_x;
	u16 video_offset_y;
} sgks_dsp_cmd_vo_default_img_setup_s;



// SGKS_DSP_CMD_VO_OSD_SETUP                            = 0x00007004,
typedef struct sgks_dsp_cmd_vo_osd_setup
{
	// cmd_code: 0x00007004 GD_VOUT_OSD_SETUP
	u32 cmd_code;

	u16 vo_id;
	u8  en;
	u8  src;

	u8  flip;
	u8  rescaler_en;
	u8  premultiplied;
	u8  global_blend;

	u16 win_offset_x;
	u16 win_offset_y;

	u16 win_width;
	u16 win_height;

	u16 rescaler_input_width;
	u16 rescaler_input_height;

	u32 osd_buf_dram_addr;

	u16 osd_buf_pitch;
	u8  osd_buf_repeat_field;
	u8  osd_direct_mode;

	u16 osd_transparent_color;
	u8  osd_transparent_color_en;
	u8  reserved;

	u32 osd_buf_info_dram_addr;//24

	///////////////////////////////////////
	u16 win_offset_x_2;
	u16 win_offset_y_2;
	u16 win_width_2;
	u16 win_height_2;
	u8  premultiplied_2;
	u8  global_blend_2;
	u16 osd_buf_pitch_2;
	u32 osd_buf_dram_addr_2;
	u8  en_2;
	u8  src_2;
	//*
	u8  osd2_direct_mode;
	u8  osd2_transparent_color_en;
	u16 osd2_transparent_color;

} sgks_dsp_cmd_vo_osd_setup_s;


// SGKS_DSP_CMD_VO_OSD_BUFFER_SETUP                     = 0x00007005,
typedef struct sgks_dsp_cmd_vo_osd_buf_setup
{
	u32 cmd_code;
	u16 vo_id;
	u16 reserved;
	u32 osd_buf_dram_addr;
	u16 osd_buf_pitch;
	u8  osd_buf_repeat_field;
	u8  reserved2;
} sgks_dsp_cmd_vo_osd_buf_setup_s;

// SGKS_DSP_CMD_VO_OSD_CLUT_SETUP                       = 0x00007006,
typedef struct sgks_dsp_cmd_vo_osd_clut_setup
{
	u32 cmd_code;
	u16 vo_id;
	u16 reserved;
	u32 clut_dram_addr;
} sgks_dsp_cmd_vo_osd_clut_setup_s;



// SGKS_DSP_CMD_VO_DISPLAY_SETUP                        = 0x00007007,
typedef struct sgks_dsp_cmd_vo_display_setup
{
	u32 cmd_code;
	u16 vo_id;
	u16 reserved;
	u32 disp_config_dram_addr;
} sgks_dsp_cmd_vo_display_setup_s;

// SGKS_DSP_CMD_VO_TV_SETUP                             = 0x00007008,
typedef struct sgks_dsp_cmd_vo_tv_setup
{
	u32 cmd_code;
	u16 vo_id;
	u16 reserved;
	u32 tv_config_dram_addr;
} sgks_dsp_cmd_vo_tv_setup_s;



// SGKS_DSP_CMD_VO_RESET                                = 0x00007009,
typedef struct sgks_dsp_cmd_vo_reset
{
	 
	u32 cmd_code;

	u16 vo_id;
	u8  reset_mixer;
	u8  reset_disp;
	u32 reset_delay;
} sgks_dsp_cmd_vo_reset_s;

// SGKS_DSP_CMD_VO_DISPLAY_CSC_SETUP                    = 0x0000700A,
typedef struct sgks_dsp_cmd_vo_display_csc_setup
{
	u32 cmd_code;
	u16 vo_id;
	u16 csc_type; // 0: digital; 1: analog; 2: hdmi
	u32 csc_parms[9];
} sgks_dsp_cmd_vo_display_csc_setup_s;


//0x0000600a,
typedef struct sgks_dsp_cmd_pip_config_default
{
	u32 cmd_code;
	u8 pip_enable;
	u8 pip_nums[2];
	u8 pip_source[2][4]; // source=1: sensor,    source=2 ocvbs in or BT656 source=3 MJPEG
	u16 pip_start_x[2][4];
	u16 pip_start_y[2][4];
	u16 pip_width[2][4];
	u16 pip_height[2][4];

	/*rescale*/
	u8 rescale_num;
	u16 rescale_width[5];
	u16 rescale_height[5];
	u8 yuv_type;
} sgks_dsp_cmd_pip_config_default_s;



// SGKS_DSP_CMD_AAA_STATISTICS_SETUP                    = 0x00002004,
typedef struct sgks_dsp_cmd_aaa_statistics_setup
{
	u32 cmd_code;
	u32 on : 8;
	u32 auto_shift : 8;
	u32 reserved : 16;
	u32 data_fifo_base;
	u32 data_fifo_limit;
	u32 data_fifo2_base;
	u32 data_fifo2_limit;
	u16 awb_tile_num_col;
	u16 awb_tile_num_row;
	u16 awb_tile_col_start;
	u16 awb_tile_row_start;
	u16 awb_tile_width;
	u16 awb_tile_height;
	u16 awb_tile_active_width;
	u16 awb_tile_active_height;
	u16 awb_pix_min_value;
	u16 awb_pix_max_value;
	u16 ae_tile_num_col;
	u16 ae_tile_num_row;
	u16 ae_tile_col_start;
	u16 ae_tile_row_start;
	u16 ae_tile_width;
	u16 ae_tile_height;
	u16 af_tile_num_col;
	u16 af_tile_num_row;
	u16 af_tile_col_start;
	u16 af_tile_row_start;
	u16 af_tile_width;
	u16 af_tile_height;
	u16 af_tile_active_width;
	u16 af_tile_active_height;
	u16 ae_pix_min_value;
	u16 ae_pix_max_value;
} sgks_dsp_cmd_aaa_statistics_setup_s;


// SGKS_DSP_CMD_AAA_STATISTICS_SETUP1                   = 0x00002110,
typedef struct sgks_dsp_cmd_aaa_statistics_setup1
{
	u32 cmd_code;
	u8  af_horizontal_filter1_mode  : 4;
	u8  af_filter1_select           : 4;
	u8  af_horizontal_filter1_stage1_enb;
	u8  af_horizontal_filter1_stage2_enb;
	u8  af_horizontal_filter1_stage3_enb;
	u16 af_horizontal_filter1_gain[7];
	u16 af_horizontal_filter1_shift[4];
	u16 af_horizontal_filter1_bias_off;
	u16 af_horizontal_filter1_thresh;
	u16 af_vertical_filter1_thresh;
	u16 af_tile_fv1_horizontal_shift;
	u16 af_tile_fv1_vertical_shift;
	u16 af_tile_fv1_horizontal_weight;
	u16 af_tile_fv1_vertical_weight;
} sgks_dsp_cmd_aaa_statistics_setup1_s;

// SGKS_DSP_CMD_AAA_STATISTICS_SETUP2                   = 0x00002111,
typedef struct sgks_dsp_cmd_aaa_statistics_setup2
{
	u32 cmd_code;
	u8  af_horizontal_filter2_mode  : 4;
	u8  af_filter2_select           : 4;
	u8  af_horizontal_filter2_stage1_enb;
	u8  af_horizontal_filter2_stage2_enb;
	u8  af_horizontal_filter2_stage3_enb;
	u16 af_horizontal_filter2_gain[7];
	u16 af_horizontal_filter2_shift[4];
	u16 af_horizontal_filter2_bias_off;
	u16 af_horizontal_filter2_thresh;
	u16 af_vertical_filter2_thresh;
	u16 af_tile_fv2_horizontal_shift;
	u16 af_tile_fv2_vertical_shift;
	u16 af_tile_fv2_horizontal_weight;
	u16 af_tile_fv2_vertical_weight;
} sgks_dsp_cmd_aaa_statistics_setup2_s;

// SGKS_DSP_CMD_AAA_STATISTICS_SETUP3                   = 0x00002118,
typedef struct sgks_dsp_cmd_aaa_statistics_setup3
{
	u32 cmd_code;
	u16 awb_tile_rgb_shift;
	u16 awb_tile_y_shift;
	u16 awb_tile_min_max_shift;
	u16 ae_tile_y_shift;
	u16 ae_tile_linear_y_shift;
	u16 af_tile_cfa_y_shift;
	u16 af_tile_y_shift;
} sgks_dsp_cmd_aaa_statistics_setup3_s;


// SGKS_DSP_CMD_MCTF_MV_STAB_SETUP                      = 0x0000200D,
typedef struct sgks_dsp_cmd_mctf_mv_stab_setup
{
	u32 cmd_code;
	u8  noise_filter_strength;
	u8  image_stabilize_strength;
	u8  still_noise_filter_strength;
	u8  reserved;
	u32 mctf_cfg_dram_addr;
} sgks_dsp_cmd_mctf_mv_stab_setup_s;


// SGKS_DSP_CMD_MCTF_GMV_SETUP                          = 0x00002010,
typedef struct sgks_dsp_cmd_mctf_gmv_setup
{
	u32 cmd_code;
	u32 enable_external_gmv;
	u32 external_gmv;
} sgks_dsp_cmd_mctf_gmv_setup_s;


// SGKS_DSP_CMD_NOISE_FILTER_SETUP                      = 0x00002009,
typedef struct sgks_dsp_cmd_noise_filter_setup
{
	u32 cmd_code;
	u32 strength;    //see above macros
} sgks_dsp_cmd_noise_filter_setup_s;

// SGKS_DSP_CMD_BLACK_LEVEL_GLOBAL_OFFSET               = 0x0000211D,
typedef struct sgks_dsp_cmd_black_level_global_offset
{
	u32 cmd_code;
	u32 global_offset_ee;
	u32 global_offset_eo;
	u32 global_offset_oe;
	u32 global_offset_oo;
	u16 black_level_offset_red;
	u16 black_level_offset_green;
	u16 black_level_offset_blue;
} sgks_dsp_cmd_black_level_global_offset_s;

// SGKS_DSP_CMD_CFA_DOMAIN_LEAKAGE_FILTER               = 0x0000200C,
typedef struct sgks_dsp_cmd_cfa_domain_leakage_filter
{
	u32 cmd_code;
	u32 enable;
	u8  alpha_rr;
	u8  alpha_rb;
	u8  alpha_br;
	u8  alpha_bb;
	u16 saturation_level;
} sgks_dsp_cmd_cfa_domain_leakage_filter_s;


// SGKS_DSP_CMD_CFA_NOISE_FILTER_INFO                        = 0x00002107,
typedef struct sgks_dsp_cmd_cfa_noise_filter_info
{
	u32 cmd_code;
	u32 enable;
	u32 center_weight_red;
	u32 center_weight_green;
	u32 center_weight_blue;
	u32 thresh_k0_red;
	u32 thresh_k0_green;
	u32 thresh_k0_blue;
	u32 thresh_k0_close;
	u32 thresh_k1_red;
	u32 thresh_k1_green;
	u32 thresh_k1_blue;
	u32 direct_center_weight_red;
	u32 direct_center_weight_green;
	u32 direct_center_weight_blue;
	u32 direct_thresh_k0_red;
	u32 direct_thresh_k0_green;
	u32 direct_thresh_k0_blue;
	u32 direct_thresh_k1_red;
	u32 direct_thresh_k1_green;
	u32 direct_thresh_k1_blue;
	u32 direct_grad_thresh;
} sgks_dsp_cmd_cfa_noise_filter_info_s;




// SGKS_DSP_CMD_VIGNETTE_COMPENSATION                   = 0x00002003,
typedef struct sgks_dsp_cmd_vignette_compensation
{
	u32 cmd_code;
	u8  enable;
	u8  gain_shift;
	u16 group_index;
	u32 tile_gain_addr;
	u32 tile_gain_addr_green_even;
	u32 tile_gain_addr_green_odd;
	u32 tile_gain_addr_blue;
} sgks_dsp_cmd_vignette_compensation_s;




// SGKS_DSP_CMD_LOCAL_EXPOSURE                          = 0x00002109,
typedef struct sgks_dsp_cmd_local_exposure
{
	u32 cmd_code;
	u16 enable;
	u16 group_index;
	u32 radius;
	u8  luma_weight_red;
	u8  luma_weight_green;
	u8  luma_weight_blue;
	u8  luma_weight_sum_shift;
	u32 gain_curve_table_addr;
	u16 black_level_offset_red;
	u16 black_level_offset_green;
	u16 black_level_offset_blue;
	u16 luma_offset;
	u16 global_offset;
} sgks_dsp_cmd_local_exposure_s;


// SGKS_DSP_CMD_COLOR_CORRECTION                        = 0x0000210C,
typedef struct sgks_dsp_cmd_color_correction
{
	u32 cmd_code;
	u8  enable;
	u8  no_interpolation;
	u8  yuv422_foramt;
	u8  uv_center;
	u32 multi_red;
	u32 multi_green;
	u32 multi_blue;
	u32 in_lookup_table_addr;
	u32 matrix_addr;
	u32 output_lookup_bypass;
	u32 out_lookup_table_addr;
	u32 group_index;
} sgks_dsp_cmd_color_correction_s;



// SGKS_DSP_CMD_RGB_TO_YUV_SETUP                        = 0x00002007,
typedef struct sgks_dsp_cmd_rgb_to_yuv_setup
{
	u32 cmd_code;
	u16 matrix_values[9];
	s16 y_offset;
	s16 u_offset;
	s16 v_offset;
	u32 group_index;
} sgks_dsp_cmd_rgb_to_yuv_setup_s;


// SGKS_DSP_CMD_CHROMA_SCALE                            = 0x0000210E,
typedef struct sgks_dsp_cmd_chroma_scale
{
	u32 cmd_code;
	u32 enable;
	u32 make_legal;
	s16 u_weight_0;
	s16 u_weight_1;
	s16 u_weight_2;
	s16 v_weight_0;
	s16 v_weight_1;
	s16 v_weight_2;
	u32 gain_curver_addr;
	u32 group_index;
} sgks_dsp_cmd_chroma_scale_s;



// SGKS_DSP_CMD_CHROMA_MEDIAN_FILTER_INFO               = 0x0000210D,
typedef struct sgks_dsp_cmd_chroma_median_filter_info
{
	u32 cmd_code;
	u32 enable;
	u32 group_index;
	u32 k0123_table_addr;
	u16 u_sat_t0;
	u16 u_sat_t1;
	u16 v_sat_t0;
	u16 v_sat_t1;
	u16 u_act_t0;
	u16 u_act_t1;
	u16 v_act_t0;
	u16 v_act_t1;
} sgks_dsp_cmd_chroma_median_filter_info_s;




// SGKS_DSP_CMD_LUMA_SHARPENING                         = 0x0000210F,
typedef struct sgks_dsp_cmd_luma_sharpening
{
	u32 cmd_code;
	u32 enable;
	u32 grad_thresh_0;
	u32 grad_thresh_1;
	u32 smooth_shift;
	u32 edge_shift;
	u32 edge_thresh;
	u32 alpha_table_addr;
	u32 group_index;
	u32 unsharp_mask[6];
	u8  clip_low;
	u8  clip_high;
	u8  max_change_down;
	u8  max_change_up;
} sgks_dsp_cmd_luma_sharpening_s;


// SGKS_DSP_CMD_LUMA_SHARPENING_FIR_CONFIG              = 0x00002121,
typedef struct sgks_dsp_cmd_luma_sharpening_FIR_config
{
	u32 cmd_code;
	u8  enable_FIR1;
	u8  enable_FIR2;
	u16 enable_FIR2_bypass_alpha;
	u32 fir0_clip_low;
	u32 fir0_clip_high;
	u32 fir1_clip_low;
	u32 fir1_clip_high;
	u32 fir2_clip_low;
	u32 fir2_clip_high;
	u32 coeff_FIR0_addr;
	u32 coeff_FIR1_addr;
	u32 coeff_FIR2_addr;
	u32 coring_table_addr;
	u32 group_index;
} sgks_dsp_cmd_luma_sharpening_FIR_config_s;


// SGKS_DSP_CMD_LUMA_SHARPENING_EDGE_CONTROL            = 0x00002130,
typedef struct sgks_dsp_cmd_luma_sharpening_edge_control
{
	u32 cmd_code;
	u32 group_index;
	u16 edge_threshold;
	u8  edge_threshold_multiplier;
	u8  wide_weight;
	u8  narrow_weight;
} sgks_dsp_cmd_luma_sharpening_edge_control_s;


// SGKS_DSP_CMD_LUMA_SHARPENING_BLEND_CONTROL           = 0x00002131,
typedef struct sgks_dsp_cmd_luma_sharpening_blend_control
{
	u32 cmd_code;
	u32 group_index;
	u16 enable;
	u8  edge_threshold_multiplier;
	u8  iso_threshold_multiplier;
	u16 edge_threshold0;
	u16 edge_threshold1;
	u16 dir_threshold0;
	u16 dir_threshold1;
	u16 iso_threshold0;
	u16 iso_threshold1;
} sgks_dsp_cmd_luma_sharpening_blend_control_s;



// SGKS_DSP_CMD_LUMA_SHARPENING_LEVEL_CONTROL           = 0x00002132,
typedef struct sgks_dsp_cmd_luma_sharpening_level_control
{
	u32 cmd_code;
	u32 group_index;
	u32 select;
	u8  low;
	u8  low_0;
	u8  low_delta;
	u8  low_val;
	u8  high;
	u8  high_0;
	u8  high_delta;
	u8  high_val;
	u8  base_val;
	u8  area;
	u16 level_control_clip_low;
	u16 level_control_clip_low2;
	u16 level_control_clip_high;
	u16 level_control_clip_high2;
} sgks_dsp_cmd_luma_sharpening_level_control_s;



// SGKS_DSP_CMD_LUMA_SHARPENING_MISC_CONTROL            = 0x00002133,
typedef struct sgks_dsp_cmd_luma_sharpening_misc_control
{
	u32 cmd_code;
	u32 group_index;
	u8  coring_control;
	u8  add_in_low_pass;
	u8  second_input_enable;
	u8  second_input_signed;
	u8  second_input_shift;
	u8  output_signed;
	u8  output_shift;
	u8  abs;
	u8  yuv;
} sgks_dsp_cmd_luma_sharpening_misc_control_s;


// SGKS_DSP_CMD_RGB_GAIN_ADJUSTMENT                     = 0x00002002,
typedef struct sgks_dsp_cmd_rgb_gain_adjust
{
	u32 cmd_code;
	u32 r_gain;
	u32 g_even_gain;
	u32 g_odd_gain;
	u32 b_gain;
	u32 group_index;
} sgks_dsp_cmd_rgb_gain_adjust_s;

// SGKS_DSP_CMD_ANTI_ALIASING                           = 0x0000211B,
typedef struct sgks_dsp_cmd_anti_aliasing_filter
{
	u32 cmd_code;
	u32 enable;
	u32 threshold;
	u32 shift;
} sgks_dsp_cmd_anti_aliasing_filter_s;




// SGKS_DSP_CMD_DIGITAL_GAIN_SATURATION_LEVEL           = 0x00002108,
typedef struct sgks_dsp_cmd_digital_gain_level
{
	u32 cmd_code;
	u32 level_red;
	u32 level_green_even;
	u32 level_green_odd;
	u32 level_blue;
	u32 group_index;
} sgks_dsp_cmd_digital_gain_level_s;




// SGKS_DSP_CMD_SET_ZOOM_FACTOR                         = 0x00002117,
typedef struct sgks_dsp_cmd_zoom_factor
{
	u32 cmd_code;
	u32 zoom_x;
	u32 zoom_y;
	u32 x_center_offset;
	u32 y_center_offset;
} sgks_dsp_cmd_zoom_factor_s;




// SGKS_DSP_CMD_BAD_PIXEL_CORRECT_SETUP                 = 0x0000200A,
typedef struct sgks_dsp_cmd_bad_pixel_correct_setup
{
	u32 cmd_code;
	u32 dynamic_bad_pixel_enable;
	u32 correction_mode;
	u32 hot_pixel_addr;
	u32 dark_pixel_addr;
	u16 shift0_4;
	u16 shift5;
	u32 static_bad_pixel_map_addr;
} sgks_dsp_cmd_bad_pixel_correct_setup_s;


// SGKS_DSP_CMD_DEMOASIC_FILTER                         = 0x0000210A,
typedef struct demoasic_filter
{
	u32 cmd_code;
	u16 enable;
	u16 group_index;
	u32 grad_clip_thresh;
	u32 grad_noise_thresh;
	u32 activity_thresh;
	u32 activity_difference_thresh;
} sgks_dsp_cmd_demoasic_filter_s;


// SGKS_DSP_CMD_FIXED_PATTERN_NOISE_CORRECTION          = 0x00002106,
typedef struct sgks_dsp_cmd_fixed_pattern_noise_correct
{
	u32 cmd_code;
	u32 fpn_pixel_mode;
	u32 row_gain_enable;
	u32 column_gain_enable;
	u32 num_of_rows;
	u16 num_of_cols;
	u16 fpn_pitch;
	u32 fpn_pixels_addr;
	u32 fpn_pixels_buf_size;
	u32 intercept_shift;
	u32 intercepts_and_slopes_addr;
	u32 row_gain_addr;
	u32 column_gain_addr;
} sgks_dsp_cmd_fixed_pattern_noise_correct_s;

// SGKS_DSP_CMD_IPCAM_REAL_TIME_ENCODE_PARAM_SETUP      = 0x00006004,
typedef struct sgks_dsp_cmd_ipcam_real_time_encode_param_setup
{
    u32 cmd_code;
    u32 enable_flags;
    u32 cbr_modify;
    u32 custom_encoder_frame_rate;
    u8  frame_rate_division_factor;
    u8  qp_min_on_I;
    u8  qp_max_on_I;
    u8  qp_min_on_P;
    u8  qp_max_on_P;
    u8  qp_min_on_B;
    u8  qp_max_on_B;
    u8  aqp;
    u8  frame_rate_multiplication_factor;
    u8  i_qp_reduce;
    u8  skip_flags;
    u8  M;
    u8  N;
    u8  p_qp_reduce;
    u8  intra_refresh_num_mb_row;
    u8  preview_A_frame_rate_divison_factor;
    u32 idr_interval;
    u32 custom_vi_frame_rate;
    u32 roi_daddr;
    s8  roi_delta[SGKS_NUM_PIC_TYPES][4];  /* 3 num pic types and 4 categories */
    u32 panic_div               :  8;
    u32 is_monochrome           :  1;
    u32 scene_change_detect_on  :  1;
    u32 reserved                : 22;
    u32 pic_size_control;
    u32 quant_matrix_addr;
    u16 P_IntraBiasAdd;
    u16 B_IntraBiasAdd;
    //tune the AQP and mode bias
    s8  intra16x16_bias;   // -64~64, clamp the negative value to -64 to avoid underflow
    s8  intra4x4_bias;     // -64~64,  clamp the negative value to -64 to avoid underflow
    s8  inter16x16_bias;   // -64~64, clamp the negative value to -64 to avoid underflow
    s8  inter8x8_bias;     // -64~64, clamp the negative value to -64 to avoid underflow

    s8  direct16x16_bias;  // -64~64, clamp the negative value to -64 to avoid underflow
    s8  direct8x8_bias;    // -64~64, clamp the negative value to -64 to avoid underflow
    s8  me_lambda_qp_offset;
    u8  reserved1;
    //s8 aqp_strength;  // 0: Automatic = existing code, 1-81: fixed strength; 1 for no AQP; -1 for inverse AQP

    //tune the deblocking parameters
    s8  alpha;     // between -6 and 6
    s8  beta;      // between -6 and 6
    u16 reserved2;

} sgks_dsp_cmd_ipcam_real_time_encode_param_setup_s;

// SGKS_DSP_CMD_IPCAM_VIDEO_ENCODE_SIZE_SETUP           = 0x00006003,
typedef struct sgks_dsp_cmd_ipcam_video_encode_size_setup
{
    u32 cmd_code;
    u32 capture_source  :  2;
    u32 Reserved1       : 30;
    u16 enc_x;
    u16 enc_y;
    u16 enc_width;
    u16 enc_height;
    u16 enable_individual_y_uv_offset; //1:enabel, 0:disable
    u16 enc_uv_x;
    u16 enc_uv_y;
} sgks_dsp_cmd_ipcam_video_encode_size_setup_s;


// SGKS_DSP_CMD_IPCAM_OSD_INSERT                        = 0x00006007,
typedef struct sgks_dsp_cmd_ipcam_osd_insert
{
    u32 cmd_code;
    u32 vo_id           :  1;
    u32 osd_enable      :  1;
    u32 osd_num_regions :  2;
    u32 reserved1       : 28;
    u32 osd_clut_dram_address[3];
    u32 osd_buf_dram_address[3];
    u16 osd_buf_pitch[3];
    u16 osd_win_offset_x[3];
    u16 osd_win_offset_y[3];
    u16 osd_win_w[3];
    u16 osd_win_h[3];
    u16 reserved2;
} sgks_dsp_cmd_ipcam_osd_insert_s;

// SGKS_DSP_CMD_H264_ENCODING_SETUP                     = 0x00001002,
typedef struct sgks_dsp_cmd_h264_encode_setup
{
    u32 cmd_code;
    u8 mode;
    u8 M;
    u8 N;
#define QLEVEL_MASK             (0x1f)
#define LEVEL_MASK              (0xE0)

#define SIMPLE_GOP              (0)
#define P2B2REF_GOP             (1)
#define P2B3REF_GOP             (2)
#define P2B3_ADV_GOP            (3)
#define HI_GOP_DRAM             (4)
#define HI_GOP_SMEM             (5)
#define NON_REF_P_GOP           (6)
#define HI_P_GOP                (7)

    u8  quality;
    u32 average_bitrate;
    u32 vbr_cntl;
    u32 vbr_setting : 8;
    u32 allow_I_adv : 8;
    u32 cpb_buf_idc : 8;
    u32 en_panic_rc : 2;
    u32 cpb_cmp_idc : 2;  // cpb compliance idc
    u32 fast_rc_idc : 4;
    u32 target_storage_space;
    u32 bits_fifo_base;
    u32 bits_fifo_limit;
    u32 info_fifo_base;
    u32 info_fifo_limit;
    u8  audio_in_freq;
    u8  vi_frame_rate;
    u8  encoder_frame_rate;
    u8  frame_sync;
    u16 initial_fade_in_gain;
    u16 final_fade_out_gain;
    u32 idr_interval;
    u32 cpb_user_size;
    u8  numRef_P;
    u8  numRef_B;
    u8  vi_frame_rate_ext;
    u8  encoder_frame_rate_ext;
    u32 pjpg_bits_fifo_base;
    u32 pjpg_bits_fifo_limit;
    u32 vbr_cbp_rate;
    u32 frame_rate_division_factor : 8;
    u32 force_intlc_tb_iframe : 1;
    u32 session_id : 4;
    u32 frame_rate_multiplication_factor : 8;
    u32 hflip : 1;
    u32 vflip : 1;
    u32 rotate : 1;
    u32 chroma_format : 1;
    u32 reserved : 7;
    u32 custom_encoder_frame_rate;
} sgks_dsp_cmd_h264_encode_setup_s;

// SGKS_DSP_CMD_JPEG_ENCODING_SETUP                     = 0x00001003,
typedef struct sgks_dsp_cmd_jpeg_encode_setup
{
    u32 cmd_code;
    u32 chroma_format;
    u32 bits_fifo_base;
    u32 bits_fifo_limit;
    u32 info_fifo_base;
    u32 info_fifo_limit;
    u32 *quant_matrix_addr;
    u32 custom_encoder_frame_rate;
    u32 mctf_mode        : 8;
    u32 is_mjpeg        : 1;
    u32 frame_rate_division_factor : 8;
    u32 session_id      : 4;
    u32 frame_rate_multiplication_factor : 8;
    u32 hflip : 1;
    u32 vflip : 1;
    u32 rotate : 1;
    u32 targ_bits_pp;
    u32 initial_ql        : 8;
    u32 tolerance        : 8;
    u32 max_recode_lp    : 8;
    u32 total_sample_pts: 8;
    u32 rate_curve_dram_addr;
    u16 screen_thumbnail_w;
    u16 screen_thumbnail_h;
    u16 screen_thumbnail_active_w;
    u16 screen_thumbnail_active_h;
} sgks_dsp_cmd_jpeg_encode_setup_s;

// SGKS_DSP_CMD_SET_WARP_CONTROL                        = 0x00002129,
typedef struct sgks_dsp_cmd_set_warp_control
{
#define    WARP_CONTROL_DISABLE    0
#define    WARP_CONTROL_ENABLE    1
    u32 cmd_code;
    u32 warp_control;
    u32 warp_horizontal_table_address;
    u32 warp_vertical_table_address;
    u32 actual_left_top_x;
    u32 actual_left_top_y;
    u32 actual_right_bot_x;
    u32 actual_right_bot_y;
    u32 zoom_x;
    u32 zoom_y;
    u32 x_center_offset;
    u32 y_center_offset;

    u8  grid_array_width;
    u8  grid_array_height;
    u8  horz_grid_spacing_exponent;
    u8  vert_grid_spacing_exponent;

    u8  vert_warp_enable;
    u8  vert_warp_grid_array_width;
    u8  vert_warp_grid_array_height;
    u8  vert_warp_horz_grid_spacing_exponent;

    u8  vert_warp_vert_grid_spacing_exponent;
    u8  binning;
    u16 reserved_2;
    s32 hor_skew_phase_inc;

    /*
        This one is used for ARM to calcuate the
        dummy window for fw, these fields should be
        zero for turbo command in case of EIS. could be
        non-zero valid value only when this warp command is send
        in non-turbo command way.
    */
    u16 dummy_window_x_left;
    u16 dummy_window_y_top;
    u16    dummy_window_width;
    u16    dummy_window_height;
    /*
        This field is used for ARM to calculate the
        cfa prescaler zoom factor which will affect
        the warping table value. this should also be zeor
        during the turbo command sending.Only valid on the
        non-turbo command time.
    */
    u16 cfa_output_width;
    u16 cfa_output_height;
} sgks_dsp_cmd_set_warp_control_s;

// SGKS_DSP_CMD_H264_ENCODE                             = 0x00003004,
typedef struct sgks_dsp_cmd_h264_encode
{
    u32 cmd_code;
    u32 bits_fifo_next;
    u32 info_fifo_next;
    u32 start_encode_frame_no;
    u32 encode_duration;
    u8  is_flush;
    u8  enable_slow_shutter;
    u8  res_rate_min;           // between 0 and 100
    s8  alpha;                  // between -6 and 6
    s8  beta;                   // between -6 and 6
    u8  en_loop_filter;         // 1 enable loop filtering.
    u8  max_upsampling_rate;
    u8  slow_shutter_upsampling_rate;

    // SPS
    u8  frame_cropping_flag;
    u8  high_profile    : 1;
    u8  reserved2       : 7;
    u16 frame_crop_left_offset;
    u16 frame_crop_right_offset;
    u16 frame_crop_top_offset;
    u16 frame_crop_bottom_offset;

    u8  num_ref_frame;
    u8  log2_max_frame_num_minus4;
    u8  log2_max_pic_order_cnt_lsb_minus4;
    u8  sony_avc        : 1;
    u8  reserved        : 7;

    u16 height_mjpeg_h264_simultaneous;
    u16 width_mjpeg_h264_simultaneous;

    u16 vui_enable                      : 1;
    u16 aspect_ratio_info_present_flag  : 1;
    u16 overscan_info_present_flag      : 1;
    u16 overscan_appropriate_flag       : 1;
    u16 video_signal_type_present_flag  : 1;
    u16 video_full_range_flag           : 1;
    u16 colour_description_present_flag : 1;
    u16 chroma_loc_info_present_flag    : 1;
    u16 timing_info_present_flag        : 1;
    u16 fixed_frame_rate_flag           : 1;
    u16 nal_hrd_parameters_present_flag : 1;
    u16 vcl_hrd_parameters_present_flag : 1;
    u16 low_delay_hrd_flag              : 1;
    u16 pic_struct_present_flag         : 1;
    u16 bitstream_restriction_flag      : 1;
    u16 motion_vectors_over_pic_boundaries_flag : 1;

    // aspect_ratio_info_present_flag
    u16 SAR_width;
    u16 SAR_height;

    // video_signal_type_present_flag
    u8  video_format;
    // colour_description_present_flag
    u8  colour_primaries;
    u8  transfer_characteristics;
    u8  matrix_coefficients;

    // chroma_loc_info_present_flag
    u8  chroma_sample_loc_type_top_field : 4;
    u8  chroma_sample_loc_type_bottom_field : 4;
    u8  aspect_ratio_idc;
    u8  reserved3;

    // bitstream_restriction_flag
    u32 max_bytes_per_pic_denom : 8;
    u32 max_bits_per_mb_denom : 8;
    u32 log2_max_mv_length_horizontal : 8;
    u32 log2_max_mv_length_vertical : 8;

    u16 num_reorder_frames;
    u16 max_dec_frame_buffering;

    u32 I_IDR_sp_rc_handle_mask : 8;
    u32 IDR_QP_adj_str : 8;
    u32 IDR_class_adj_limit : 8;
    u32 reserved_1 : 8;
    u32 I_QP_adj_str : 8;
    u32 I_class_adj_limit : 8;
    u32 firstGOPstartB : 8;
    u32 au_type : 8;
    //tune the AQP and mode bias
    s8  intra16x16_bias;   // -64~64, clamp the negative value to -64 to avoid underflow
    s8  intra4x4_bias;     // -64~64,  clamp the negative value to -64 to avoid underflow
    s8  inter16x16_bias;   // -64~64, clamp the negative value to -64 to avoid underflow
    s8  inter8x8_bias;     // -64~64, clamp the negative value to -64 to avoid underflow

    s8  direct16x16_bias;  // -64~64, clamp the negative value to -64 to avoid underflow
    s8  direct8x8_bias;    // -64~64, clamp the negative value to -64 to avoid underflow
    s8  me_lambda_qp_offset;
    s8  reserved4;
} sgks_dsp_cmd_h264_encode_s;

// SGKS_DSP_CMD_MJPEG_ENCODE                            = 0x00004006,
typedef struct sgks_dsp_cmd_mjpeg_capture
{
    u32 cmd_code;
    u32 bits_fifo_next;
    u32 info_fifo_next;
    u32 start_encode_frame_no;
    u32 encode_duration;
    u8  framerate_control_M;
    u8  framerate_control_N;
    u16 reserve;
} sgks_dsp_cmd_mjpeg_capture_s;

// SGKS_DSP_CMD_ENCODING_STOP                           = 0x00003007,
typedef struct sgks_dsp_cmd_h264_encode_stop
{
    u32 cmd_code;
#define H264_STOP_IMMEDIATELY       0
#define H264_STOP_ON_NEXT_IP        1
#define H264_STOP_ON_NEXT_I         2
#define H264_STOP_ON_NEXT_IDR       3
#define EMERG_STOP                  0xff
    u32 stop_method;
} sgks_dsp_cmd_h264_encode_stop_s;



// SGKS_DSP_CMD_DECODE_RESCALE                = 0x00005018,
typedef struct sgks_dsp_cmd_rescale
{
	u32 cmd_code;
	u8 rescale_total_num;
	u16 rescale_width[5];
	u16 rescale_height[5];
} sgks_dsp_cmd_rescale_s;

// SGKS_DSP_CMD_DECODE_STOP                             = 0x00005009,
typedef struct sgks_dsp_cmd_h264_decode_stop
{
	u32 cmd_code;
	u8 stop_flag;
} sgks_dsp_cmd_h264_decode_stop_s;

// SGKS_DSP_CMD_H264_DECODING_SETUP                     = 0x00001004,
typedef struct sgks_dsp_cmd_h264_decode_setup
{
	u32 cmd_code;
	u32 bits_fifo_base;
	u32 bits_fifo_limit;
	u32 fade_in_pic_addr;
	u32 fade_in_pic_pitch;
	u32 fade_in_alpha_start;
	u32 fade_in_alpha_step;
	u32 fade_in_total_frames;
	u32 fade_out_pic_addr;
	u32 fade_out_pic_pitch;
	u32 fade_out_alpha_start;
	u32 fade_out_alpha_step;
	u32 fade_out_total_frames;
	u8  cabac_to_recon_delay;
	u8  forced_max_fb_size;
} sgks_dsp_cmd_h264_decode_setup_s;

// SGKS_DSP_CMD_JPEG_DECODING_SETUP                     = 0x00001005,
typedef struct sgks_dsp_cmd_jpeg_decode_setup
{
	u32 cmd_code;
	u32 bits_fifo_base;
	u32 bits_fifo_limit;
	u32 cross_fade_alpha_start;
	u32 cross_fade_alpha_step;
	u32 cross_fade_total_frames;
	u8  background_y;
	u8  background_cb;
	u8  background_cr;
	u8  reserved;
	u16 max_vo_width;
	u16 max_vo_height;
} sgks_dsp_cmd_jpeg_decode_setup_s;

// SGKS_DSP_CMD_RESCALE_POSTPROCESSING                  = 0x00005005,
typedef struct sgks_dsp_cmd_rescale_postproc
{
	u32 cmd_code;
	u16 input_center_x;
	u16 input_center_y;
	u16 display_win_offset_x;
	u16 display_win_offset_y;
	u16 display_win_width;
	u16 display_win_height;
	u32 zoom_factor_x;
	u32 zoom_factor_y;
	u8  apply_yuv;
	u8  apply_luma;
	u8  apply_noise;
	u8  pip_enable;
	u16 pip_x_offset;
	u16 pip_y_offset;
	u16 pip_x_size;
	u16 pip_y_size;
	u16 sec_display_win_offset_x;
	u16 sec_display_win_offset_y;
	u16 sec_display_win_width;
	u16 sec_display_win_height;
	u32 sec_zoom_factor_x;
	u32 sec_zoom_factor_y;

	u32 reserved            : 31;
	u32 animated_rotation   :  1;

	u32 warp_horizontal_table_address;
	u32 warp_vertical_table_address;

	u8  grid_array_width;
	u8  grid_array_height;
	u8  horz_grid_spacing_exponent;
	u8  vert_grid_spacing_exponent;
	u8  vert_warp_grid_array_width;
	u8  vert_warp_grid_array_height;
	u8  vert_warp_horz_grid_spacing_exponent;
	u8  vert_warp_vert_grid_spacing_exponent;
} sgks_dsp_cmd_rescale_postproc_s;



// SGKS_DSP_CMD_H264_DECODE                             = 0x00005002,
typedef struct sgks_dsp_cmd_h264_decode
{
	u32 cmd_code;
	u32 bits_fifo_start;
	u32 bits_fifo_end;
	u32 num_pics;
	u32 num_frame_decode;
	u32 first_frame_display;
	u32 fade_in_on;
	u32 fade_out_on;
} sgks_dsp_cmd_h264_decode_s;


// SGKS_DSP_CMD_H264_DECODE_BITS_FIFO_UPDATE            = 0x00005006,
typedef struct sgks_dsp_cmd_h264_decode_bits_fifo_update
{
	u32 cmd_code;
	u32 bits_fifo_start;
	u32 bits_fifo_end;
	u32 num_pics;
} sgks_dsp_cmd_h264_decode_bits_fifo_update_s;

// SGKS_DSP_CMD_JPEG_DECODE                             = 0x00005003,
typedef struct sgks_dsp_cmd_jpeg_decode
{
	u32 cmd_code;
	u32 bits_fifo_start;
	u32 bits_fifo_end;
	u8  main_rotation;
	u8  ycbcr_position;
	u16 reserved;
	u32 frame_duration;
	u32 num_frame_decode;
	u8  already_decoded;
	u8  sec_rotation;
} sgks_dsp_cmd_jpeg_decode_s;

//    SGKS_DSP_CMD_IPCAM_SWITCH_SRC                         = 0x0000600B,
typedef struct sgks_dsp_cmd_switch_src
{
    u32 cmd_code;
    u8  switch_src;
}sgks_dsp_cmd_switch_src_s;

// SGKS_DSP_CMD_H264_ENC_USE_TIMER                      = 0x00001008,
typedef struct sgks_dsp_cmd_vi_timer_mode
{
	u32 cmd_code;
	u8  timer_scaler;
	u8  display_opt;
	u8  video_term_opt; // 0 terminate with frame wait, 1 reset icore, and terminate right away
	u8  reserved;
} sgks_dsp_cmd_vi_timer_mode_s;

// SGKS_DSP_CMD_RESET_OPERATION                         = 0x00001006,
typedef struct sgks_dsp_cmd_reset_operation_s
{
	u32 cmd_code;
} sgks_dsp_cmd_reset_operation_s;


#ifdef  __cplusplus
}
#endif

#endif





